1. Field of the Invention
The invention relates generally to biasing the substrate of a semiconductor integrated circuits containing field effect devices, and more particularly, to a method of and apparatus for controlling substrate bias voltage to prevent latching up of parasitic transistors at the time of circuit turn on.
2. Description of the Prior Art
The present invention is applicable to a MOS type semiconductor memory comprising a MOS transistor, and particularly to a MOS dynamic RAM (Random Access Memory).
A description is made hereinafter as to the MOS dynamic RAM which is a background of the present invention.
FIG. 1A is a block diagram showing an example of a simplified circuit of a conventional 1 M bit dynamic RAM (Random Access Memory) having 1048576 memory cells. Referring to FIG. 1A, a summary of the basic operation of the dynamic RAM will be hereinafter described.
A clock generator 10 receives an RAS (Row Address Strobe) signal, CAS (Column Address Strobe) signal from a CPU (Central Processing Unit) and generates clock signals .phi..sub.1 and .phi..sub.2. In the normal read/write operation of the dynamic RAM, an address buffer 21 receives external address inputs. A.sub.0 to A.sub.9 on a time share basis and applies internal address signals A.sub.0 to A.sub.9 on a time share basis to a row decoder 22 and a column decoder 23. The row decoder 22 and the column decoder 23 decode the internal address signals A.sub.0 to A.sub.9 and apply the decoded signals to a memory cell array 25 and an I/O control 24. The writing operation of the input data and the reading operation of the output data are carried out for a memory cell having the address designated as described above. The data in buffers 26 receives the input data and transfers the input data to the memory cell array 25 via the I/O control 24 and the sense amplifiers in response to a clock signal. On the other hand, the data out buffers 27 receive the data from the memory cell array 25 via the sense amplifiers and the I/O control 24 and outputs the output data in response to the clock signal.
FIG. 1B is a block diagram showing a major portion of a conventional dynamic RAM.
Referring to FIG. 1B, the major portion of dynamic RAM comprises an array comprising a plurality of memory cells serving as memory portions, row decoder and a column decoder for selecting an address of each memory cell, and a peripheral circuit portion comprising a sense amplifier connected to data in/out buffers. The plurality of memory cells serving as memory portions are each connected to intersection points of word lines connected to the row decoder and bit lines connected to the column decoder, these word and bit lines constituting a matrix. The above-mentioned array is thus implemented.
Next, an operation of the dynamic RAM is described. When a word line and a bit line are selected by the row decoder and the column decoder in response to a row address signal and a column address signal externally provided, a memory cell at the intersection point of the word line and the bit line is selected, and information is read from or written in the memory cell through the sense amplifier. As to the detail explanation of dynamic RAM, U.S. Pat. No. 3,940,747, entitled "High Density, High Speed Random Access Read-Write Memory" can be referred to.
In this invention, other portion than memory cell 25 in FIG. 1A is to be defined as a peripheral circuit hereinafter.
FIG. 2 is a drawing showing a cross section of a memory cell in the memory cell portion 25 and an equivalent circuit thereof.
The memory cell portion of the dynamic RAM is formed of a transistor and a capacitance. As shown in FIG. 2, the transistor comprises a MOS transistor 31 of an n channel type and the capacitance comprises a cell plate 32 and an n.sup.+ layer 33.
Fig. 3A is a drawing showing a cross section of a peripheral circuit such as row and column address buffer 21, clock generator circuit 10 and so on, and an equivalent circuit thereof. The peripheral circuit portion is generally formed of a CMOS inverter.
FIG. 3B is an equivalent circuit of the peripheral circuit shown in FIG. 3A and prepared for explaining parasitic bipolar transistors and a parasitic capacitance being parasitic on the MOS dynamic RAM.
Referring to FIG. 3A and 3B, a substrate bias voltage V.sub.BB is applied to a p type silicon substrate 20 through a substrate bias conductor 4. The substrate bias voltage V.sub.BB is generated from a V.sub.BB generating circuit 3 (shown in FIG. 4) provided on a RAM chip. A p channel MOS transistor is formed in an n-well 21 formed in the p type silicon substrate 20. An n.sup.+ diffused layer 22 serves to fix a voltage of n-well 21 to a supply voltage V.sub.CC, which is connected to a V.sub.CC power supply conductor. An n.sup.+ diffused layer 23 is formed in the p type silicon substrate 20 and it is connected to the V.sub.CC power supply conductor. An n.sup.+ diffused layer 24 is formed in the p type silicon substrate 20 and it is connected to a ground conductor V.sub.SS.
As seen from the drawing, a p-n junction capacitance C well formed between the n-well 21 and the p type silicon substrate 20 and a p-n junction capacitance Cn.sup.+ formed between the n.sup.+ diffused layer 23 and the p type silicon substrate 20 form a component of the parasitic capacitance.
Referring to FIG. 3B, a mechanism of the latching-up is explained. The peripheral circuit comprises phantom bipolar transistor Tr.sub.1 (pnp transistor) coupled between the power supply conductor V.sub.CC and V.sub.BB generating circuit through resistance R.sub.2, a phantom bipolar transistor Tr.sub.2 (npn transistor) coupled between the power supply conductor V.sub.CC through a resistance R.sub.1 and the ground conductor V.sub.SS, parasitic capacitance 6 coupled between the power supply conductor V.sub.CC and the V.sub.BB generating circuit, and a substrate bias V.sub.BB generating circuit coupled between the power supply conductor V.sub.CC and the ground conductor V.sub.SS. The substrate bias V.sub.BB generating circuit is provided to provide a predetermined negative bias voltage to the substrate.
Tr.sub.1 comprises a p.sup.+ diffusion layer in an n-well, an n.sup.+ diffusion layer 22 in the n-well and the substrate itself. Tr.sub.2 comprises an n.sup.+ diffusion layer 24, the substrate itself and n.sup.+ diffusion layer 22 in the n-well. The C well is formed between n-well 21 and the substrate 20. V.sub.BB generating circuit usually keeps the substrate at -3 V. A reversed bias is applied between a base and an emitter of the transistor Tr.sub.2. Transistor Tr.sub.2 is in off state. Therefore, no voltage is applied between the base and the emitter of transistor Tr.sub.1 and transistor Tr.sub.1 is also in off state. When the substrate bias voltage V.sub.BB becomes a certain positive value, forward bias voltage is applied to the p-n junction and the latching-up occurs. Following is an example that causes the V.sub.BB to become a positive value. When power supply is raised from 0 volt to the predetermined positive value, for example, 5 volts, V.sub.BB can be a positive value due to a capacitance coupling caused by the parasitic capacitance 6. When V.sub.BB becomes a positive value, forward bias voltage is applied between the base and the emitter of the transistor Tr.sub.2 and transistor Tr.sub.2 turns on. A current flows from the power supply conductor V.sub.CC to the ground conductor V.sub.SS through the resistance R.sub.1 and the transistor Tr.sub.2. As there is the resistance R.sub.1 and the substrate, potential drops occur and a forward bias voltage is applied between the base and the emitter of the transistor Tr.sub.1. As a result, the transistor Tr.sub.1 turns on. A current flows to the base of the transistor Tr.sub.2 and the Tr.sub.2 is kept turning on (corresponding to the state .circle. shown in FIG. 3B). As there is the resistance R.sub.1 in the substrate, Tr.sub.1 is kept turning on (corresponding to the state .circle. shown in FIG. 3B). States .circle. and .circle. occurs continuously and a current continues to flow from the power supply conductor V.sub.CC to the ground conductor V.sub.SS. This phenomenon is called a latch-up.
FIG. 4 is a drawing showing a typical V.sub.BB generating circuit. V.sub.BB generating circuit comprises a ring oscillator consisting of an odd numbers of inverters connected in series in a ring manner and a charge pump circuit consisting of two diode connected n-channel MOS transistors Q.sub.20, Q.sub.21. The oscillator is connected with the charge pump at a node N.sub.A through a capacitor C.sub.A. MOS transistor Q.sub.20 is connected between the node N.sub.A and a ground conductor V.sub.SS. A MOS transistor Q.sub.21 is connected between the node N.sub.A and the substrate bias conductor V.sub.BB.
FIG. 5 is a timing diagram showing potential change of V.sub.BB and prepared to explain an operation of the V.sub.BB generating circuit. .phi. is a potential at the node .phi. (shown in FIG. 4). N.sub.A is a potential at the node N.sub.A (shown in FIG. 4), and V.sub.BB is a potential of the V.sub.BB conductor.
When time is t.sub.0, potential of the node N.sub.A and the V.sub.BB conductor is 0 volt. When time is t.sub.1, potential at .phi. is raised from "L" to "H". The potential at node N.sub.A is boosted to the positive value due to the capacitance coupling of the capacitor C.sub.A. Then MOS transistor Q.sub.20 begins to turn on and the potential at node N.sub.A begins to be lowered from the raised positive voltage to 0 volt. When the potential at node N.sub.A is V.sub.TH (t=t.sub.2), corresponding to the threshold voltage of the MOS transistor Q.sub.20, MOS transistor Q.sub.20 turns off. The potential at node N.sub.A is kept at the V.sub.TH level. As MOS transistor Q.sub.21 is kept at off state during above operation, the potential of the V.sub.BB conductor is kept 0 volt. When time is t.sub.3, the potential at .phi. is lowered from "H" to "L". The potential at N.sub.A is lowered also due to the capacitance coupling of the capacitor C.sub.A. Then MOS transistor Q.sub.21 begins to turn on, and the current flows from the V.sub.BB conductor to the node N.sub.A. The potential at the node N.sub. A begins to be raised to 0 volt and the potential at the V.sub.BB conductor is lowered a little to the negative voltage. When the potential at node N.sub.A is -V.sub.TH, (time t=t.sub.4), MOS transistor Q.sub.21 turns off. The potential at node N.sub.A is kept at -V.sub.TH and the MOS transistor Q.sub.20 is kept at the off state during above operation. By repeating above operation, the potential of the V.sub.BB conductor gradually becomes negative and theoretically, it saturates at the level of--(V.sub.CC -2V.sub.TH).
The substrate bias circuit is provided on the dynamic RAM for the following purposes.
The negative substrate bias is necessary to prevent the electron injection problem. In dynamic RAM circuits, some n-p junctions become a little bit (max. -2 volts) forward biasing condition if the substrate potential is 0 volt. Forward biasing condition occurs in two cases. One case occurs in data input circuits which are in general the electro-static discharge absorbing circuit. As shown in FIG. 6A, input signals such as address and RAS/CAS control signals (showing in FIG. 1A) are supplied to n-p junctions from the outside of a memory chip. At that time, the input pulse gives rise to the undershoot because of the parasitic capacitance. This voltage undershoot up to -2 volts is usually allowed as shown in FIG. 6B. In other words, the commercial dynamic DRAM should be operated normally for the undershooted input pulses up to -2 volts.
The other case occurs in the capacitance coupled circuits (FIG. 6C). In this case, voltage undershoot occurs at the n-p junction as shown in FIG. 6D.
Therefore in both cases, if the p-substrate was not biased to more negative than -2 volts, these n-p junctions will become forward bias condition for a diode during the period of the undershoot. This means that a large quantity of electrons are injected in the substrate. Some of them will drift toward the memory cell capacitor and cause the "High" to "Low" error.
The most effective and popular way to prevent this problem is the application of negative (&gt; -2 volts) bias to the substrate. If the substrate is biased to, for example, -3 volts, forward bias condition will never occur.
There are some another advantages of the negative bias. The MOS circuit operation speed is improved because of the reduction of the junction capacitance. The width of the depletion layer becomes wider when the substrate is biased to negative potential for n-channel MOS transistor. The junction capacitance falls off at the inverse root of the reverse bias V.sub.R between the junction. EQU C.sub.junction .alpha. (V.sub.R) -1/2
The decrease of the junction capacitance is also useful to decrease the bit line capacitance. Bit line capacitances is one of the key parameters for dynamic RAM operation. Smaller bit line capacitance is better to improve the noise margin of dynamic RAM.
A conventional substrate bias circuit of a MOS dynamic RAM is disclosed in IEDM 85 pp. 504-508, entitled "Static and Transient Latch-up Hardness in N-well CMOS on-chip Substrate Bias Generator" by D. Takacs et al.
FIG. 7 shows the substrate bias circuit disclosed therein. The substrate bias circuit comprises a V.sub.CC power supply conductor 1 to which the supply voltage V.sub.CC is applied, a ground conductor 2 to which a reference voltage V.sub.SS of a ground level (0V) is applied, a substrate bias V.sub.BB generating circuit 3 provided on the chip of the MOS dynamic RAM (referred to as a RAM chip hereinafter), a substrate bias conductor 4, a substrate bias voltage control circuit 5, and a capacitor 6 existing between the V.sub.CC power supply conductor 1 and the substrate bias conductor 4. The capacitor 6 corresponds to the parasitic capacitance described in connection with FIG. 3A and 3B.
The substrate bias voltage V.sub.BB generating circuit 3 generates a negative substrate bias V.sub.BB. The substrate bias voltage V.sub.BB as the output of the V.sub.BB generating circuit 3 is applied to the substrate bias conductor 4. The substrate bias voltage control circuit 5, made of MOS transistor, having its gate and drain connected to the substrate bias conductor 4 and its source connected to the ground conductor 2.
Now a description is made of an operation of the substrate bias circuit which is performed when the supply voltage V.sub.CC is turned on in reference to FIG. 8.
The supply voltage V.sub.CC starts to be applied at a time t.sub.0. The supply voltage V.sub.CC gradually rises from 0V toward a preset positive value for example, 5V from the time t.sub.0 to a time t.sub.2. At this time, the substrate bias voltage V.sub.BB is boosted up from 0V to a positive value by capacitance coupling of the capacitor 6. The value of the V.sub.BB exceeds a threshold voltage V.sub.TH of the MOS transistor 5 and forms V.sub.BB spike at a time t.sub.1. As a result, the MOS transistor 5 turns on and the value of the V.sub.BB is prevented from being boosted up above the V.sub.TH. Therefore, the value of the V.sub.BB is clamped at the value of the V.sub.TH in a period from the time t.sub.1 to a time t.sub.3. At the time t.sub.3, the V.sub.BB generating circuit 3 starts to be operated. The value of the V.sub.BB falls to a negative value and at a time t.sub.4 the value of the V.sub.BB becomes stable.
The conventional substrate bias circuit is structured as described above. Therefore, it involves a disadvantage that the level at which the substrate bias voltage V.sub.BB is clamped when the supply voltage V.sub.CC is turned on depends on the threshold voltage V.sub.TH of the MOS transistor 5.
The value of the V.sub.TH must be V.sub.TH &lt;V.sub.F (V.sub.F is a forward voltage of the p-n junction and approximately 0.6V). The reason for this is that if the value of the V.sub.TH of the MOS transistor 5 is V.sub.TH &gt;V.sub.F, the p-n junction formed between the p type silicon substrate 20 and the n.sup.+ diffused layer 24 is caused to be in a forward bias (referring to FIG. 3) when the supply voltage V.sub.CC is turned on. More specifically, this induces the latch-up in the CMOS when the p-n junction is caused to be in the forward bias.
In FIG. 8, an operating point of the MOS transistor 5 in the period from the time t.sub.1 to the time t.sub.3 is in a saturation region in which the voltage between the gate and the source is around V.sub.TH. Therefore, the MOS transistor 5 cannot be in a sufficiently low impedance state. As a result, when the power supply is turned on to cause the supply voltage V.sub.CC to rise steeply, the V.sub.BB is boosted up by the capacitance coupling of the capacitor 6. Consequently, the value of the V.sub.BB could change instantaneously to a positive value above the V.sub.TH around the time t.sub.1. The reason for such change is that the effect of boosting up of the V.sub.BB by the capacitance coupling of the capacitor 6 exceeds the impedance of clamping the V.sub.BB to the level of the V.sub.TH by the MOS transistor 5.
In this case, the p-n junction between of the p type silicon substrate 20 and the n.sup.+ diffused layer 24 is caused to be in the forward bias (referring to FIG. 3B), resulting in latch-up in the CMOS.